Metal-oxide-semiconductor length is reduced. To sustain such aggressive downscaling,

Metal-oxide-semiconductor
field effect transistors (MOSFETs) have driven and dominated the semiconductor
industry since their first fabrication in 1960 1.  In 1965, Gordon Moore observed that the number
of transistors in an integrated circuit (IC) was doubling every two years 2
as a result of a dramatic scaling of the feature sizes. However, the device
electrostatics or the ability of the transistor’s gate electrode to control the
channel potential is degraded when the channel length is reduced. To sustain
such aggressive downscaling, enormous research investment is made for every new
generation of integrated circuits. Scaling transistors beyond the 14 nm technology
node has become quite challenging due to excessive increase in the power
density. The
most effective way to control the power density is to scale down the supply
voltage (VDD) as the dynamic power displays a quadratic
dependence on VDD. However, VDD scaling has
significantly slowed down beyond the 90 nm technology node. The problem lies in
the 60 mV/dec subthreshold swing (SS)
limitation of any device based on charge flow over an energy barrier 3. This fundamental limitation is one of the most
important and enduring challenges to VDD scaling which makes it impossible to scale down the supply voltage without
dramatically increasing the static power consumption. The anticipatable end of complementary-metal-oxide-semiconductor
(CMOS) scaling is an illustrious reason for the exploration of alternative
transistor technologies. As a first step, it is expected that beyond-CMOS
devices might perform specialized functions in chips that are still primarily
comprised of CMOS transistors. Among several beyond CMOS devices discussed in
the literature 4, tunnel field effect transistors (TFETs) stands out as a
leading candidate for low-power logic applications 5, due to the projected
ability to achieve sub 60 mV/dec subthreshold swings at room temperature.
Although, aggressive scaling of feature size enabled smaller and faster individual
logic elements, computational speed of a digital system is limited by the communication
between its different parts. This bottleneck is identified as one of the ostentatious
challenges in the progress of integrated electronics 6. The universal goal of
a device and circuit design for digital operation is to obtain the highest
possible switching speed for the lowest overall static and dynamic power dissipation
in a cost-effective way. As the speed of electronic circuits approaches 10 Gbps
and beyond, the volume of chip-to-chip and on-chip communication skyrockets. Traditional
copper wires are efficient at short distances, but they suffer excessive power dissipation
and delay in global lines, and cannot cope with the ever growing bandwidth demand.
Optical interconnects have shown tremendous promise in recent years for
replacing electrical wires for both on-chip and off-chip communications 7. The
idea of bringing high speed optical signals directly to CMOS chip offers
opportunities for using light to aid electrical functions in novel ways. One
primary challenge lies in developing low energy per bit receivers, of the order
of 10 fJ / bit or less, for on chip communication 8. Achieving this requires
low capacitance photodiodes and tight integration with low capacitance detector.
In this context, a detector based on a MOSFET structure represents a highly
practical and uniquely scalable optoelectronic component 9. Light induced
current modulation in optical MOSFETs can be achieved either by photo-generated
carriers in the channel under direct illumination or by photo-gating effect. A photo-gated MOSFET is a promising device,
which utilizes the photo-gating action of optically generated electron–hole
pairs (EHPs) to exhibit light induced conductivity modulation. Light detection
based on photo-gating effect offers several advantages in terms of speed and
superior noise performance 9.